In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. As the size of individual transistors is reduced with every new circuit generation, the space between adjacent gates in the transistors is becoming the limiting factor for further scaling. Specifically, the reduction in space between adjacent gates results in a smaller amount of area that can be used for silicide formation of contacts. With smaller contact area, contact resistance cannot be sufficiently reduced.
The space between adjacent gates is limited not only by gate pitch, but also be gate length and spacer width. Gate length cannot be easily reduced due to sub-threshold leakage increasing exponentially with smaller gate size and due to short channel effects degrading device characteristics. Therefore, it is desirable to reduce spacer width.
However, in typical processing spacers are necessary to offset the source/drain implants from the channel region. After implants are formed, the thermal annealing process typically causes the implanted junction profile to diffuse under the gate. If the implanted junctions have not been offset appropriately during implant, diffusion under the gate can cause an electrical short. Therefore, the implant offset is vital to keep the implanted junctions away from the channel region.
Accordingly, it is desirable to provide integrated circuits and methods for forming integrated circuits with improved spacers. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits which form spacers having maximum thickness at an elevated section to offset implants and a reduced thickness at a base section to maximize silicided contact area. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.